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Giải thích chi tiết về linh kiện  2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
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NBSG53A
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2
VTD
CLK
CLK
VTCLK
VCC
R
VTCLK
D
D
VTD
VCC
VEE
SEL
OLS
Q
Q
A
B
C
D
12
3
4
Figure 1. BGA−16 Pinout (Top View)
VTD
D
D
VTD
VCC
R
SEL OLS
VEE
Q
Q
VCC
VTCLK
CLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG53A
Exposed Pad
(EP)
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
Description
C2
1
VTCLK
Internal 50
W Termination Pin. See Table 4.
C1
2
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
B1
3
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
B2
4
VTCLK
Internal 50
W Termination Pin. See Table 4.
A1
5
VTD
Internal 50
W termination pin. See Table 4.
A2
6
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
A3
7
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
A4
8
VTD
Internal 50
W Termination Pin. See Table 4.
D1,B3
9,16
VCC
Positive Supply Voltage
B4
10
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50
W Resistor to
VTT = VCC − 2 V.
C4
11
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50
W Resistor to
VTT = VCC − 2 V.
C3
12
VEE
Negative Supply Voltage
D4
13
OLS*
Input
Input Pin for the Output Level Select (OLS). See Table 2.
D3
14
SEL
LVECL,
LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 k
W to VEE.
D2
15
R
LVECL,
LVCMOS,
LVTTL Input
Reset D Flip−Flop. Internal 75 k
W to VEE.
N/A
EP
Exposed Pad. (Note 1)
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat−sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination volt-
age, and if no signal is applied then the device will be susceptible to self−oscillation.
3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2KW resistor should be connected from OLS pin to VEE.


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   2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip?묯lop/Clock Divider with Reset and OLS
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