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KFH1G16U2M-DIB bảng dữ liệu(PDF) 8 Page - Samsung semiconductor |
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KFH1G16U2M-DIB bảng dữ liệu(HTML) 8 Page - Samsung semiconductor |
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8 / 93 page  OneNAND512/OneNAND1GDDP FLASH MEMORY 8 3. PIN DESCRIPTION NOTE: Do not leave power supply(VCC, VSS) disconnected. Pin Name Type Nameand Description Host Interface A15~A0 I Address Inputs - Inputs for addresses during read operation, which are for addressing BufferRAM & Register. DQ15~DQ0 I/O Data Inputs/Outputs - Inputs data during program and commands during all operations, outputs data during memory array/ register read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. INT O Interrupt Notifying Host when a command has completed. It is open drain output with internal resistor(~50kohms). After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float to hi-z condition even when the chip is deselected or when outputs are disabled. RDY O Ready Indicates data valid in synchronous read modes and is activated while CE is low CLK I Clock CLK synchronizes the device to the system bus frequency in synchronous read mode. The first rising edge of CLK in conjunction with AVD low latches address input. WE I Write Enable WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge AVD I Address Valid Detect Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one clock cycle. > Low : for asynchronous mode, indicates valid address ;for burst mode, causes starting address to be latched on rising edge on CLK > High : device ignores address inputs RP I Reset Pin When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up and bootloading. CE I Chip Enable CE-low activates internal control logic, and CE-high deselects the device, places it in standby state, and places A/DQ in Hi-Z OE I Output Enable OE-low enables the device’s output data buffers during a read cycle. Power Supply VCC-Core/Vcc Power for OneNAND Core This is the power supply for OneNAND Core. VCC-IO/Vccq Power for OneNAND I/O This is the power supply for OneNAND I/O Vcc-IO is internally connected to Vcc-Core, thus should be connected to the same power supply. VSS Ground for OneNAND etc. DNU Do Not Use Leave it disconnected. These pins are used for testing. NC No Connection Lead is not internally connected. |
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