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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADS5120 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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ADS5120 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 18 page  ADS5120 4 SBAS247B www.ti.com PARAMETER CONDITION MIN TYP MAX UNITS Maximum Conversion Rate 1 40 MSPS Clock Duty Cycle DCASEL Enabled 30 to 70 % Data Latency(1) 7 Clk Cycles Clock ↓ to Data Valid tDO(1) 810 ns OE ↓ to Outputs Enabled tEN(1) 8ns OE ↑ Rising to Outputs Tri-Stated tDIS 8ns Aperture Delay 1ns Aperture Uncertainty (Jitter) 2 ps, r ms NOTE: (1) See Timing Diagram. ADS5120 TARGETED AC CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog input at –0.5dBFS Input Span, Internal voltage reference, TMIN = 0°C, TMAX = 70°C, and typical values are at TA = 25°C, unless otherwise noted. ADS5120 SWITCHING CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog input at –0.5dBFS Input Span, Internal voltage reference, TMIN = 0°C, TMAX = 70°C, and Typical values are at TA = 25°C, unless otherwise noted. PARAMETER CONDITION MIN TYP MAX UNITS Signal-to-Noise Ratio (SNR) fIN = 3.5MHz 55 58 dB fIN = 10MHz 55 58 dB fIN = 20MHz 58 dB Signal-to-Noise and Distortion (SINAD) fIN = 3.5MHz 55 57 dB fIN = 10MHz 55 57 dB fIN = 20MHz 57 dB Effective Number of Bits (ENOB) fIN = 3.5MHz 8.8 9.2 Bits fIN = 10MHz 8.8 9.2 Bits fIN = 20MHz 8.8 9.2 Bits Spurious-Free Dynamic Range (SFDR) fIN = 3.5MHz 65 73 dBc fIN = 10MHz 65 72 dBc fIN = 20MHz 72 dBc 2nd-Harmonic Distortion (HD2) fIN = 3.5MHz 68 79 dBc fIN = 10MHz 68 80 dBc fIN = 20MHz 80 dBc 3rd-Harmonic Distortion (HD3) fIN = 3.5MHz 65 76 dBc fIN = 10MHz 65 78 dBc fIN = 20MHz 73 dBc 2-Tone Intermod. Distortion (IMD) f1 = 4.43MHz, f2 = 4.53MHz at –6.5dB –69 dBFS Channel-to-Channel Crosstalk fIN = 10MHz, DRVDD = 3.3V 89 dB Large-Signal Bandwidth (FPBW) 300 MHz Over-Voltage Recovery Time(1) 20 ns Differential Gain(1) ±1% Differential Phase(1) ±0.25 Degree NOTE: (1) Assured by design. TIMING DIAGRAM (Per ADC Channel) Analog Input CLK OE D[9:0] S – 6 S – 7S – 5S – 4S – 3S – 2S – 1S1 S2 t DO t DIS t EN Sample 1 Sample 2 910 8 7 6 5 4 3 2 1 |
Số phần tương tự - ADS5120 |
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Mô tả tương tự - ADS5120 |
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