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ADMV7810CHIPS bảng dữ liệu(PDF) 5 Page - Analog Devices

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Data Sheet
ADMV7810
Rev. 0 | Page 5 of 17
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
3
2
1
RFIN
GND
GND
GND
GND
20
21
22
RFOUT
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ADMV7810
TOP VIEW
(Not to Scale)
Figure 2. Pad Configuration
Table 4. Pad Function Descriptions
Pad No.
Mnemonic
Description
1, 3, 5, 7, 9, 11, 13,
15, 17, 19, 20, 22,
25, 27, 29, 31, 33,
35, 37, 39
GND
Ground Connection (See Figure 3).
2
RFIN
RF Input. AC-couple RFIN and match it to 50 Ω (See Figure 4).
4, 8, 12, 16
VGG1A to
VGG4A
First Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external
components, see Figure 46.
6, 10, 14, 18
VDD1A to
VDD4A
First Stage Drain Bias Voltage for the Power Amplifier (See Figure 5).
21
RFOUT
RF Output. AC-couple RFOUT and match it to 50 Ω (see Figure 6).
23
VREF
Reference Voltage for the Power Detector (See Figure 7). VREF is the dc bias of the diode biased
through an external resistor used for temperature compensation of VDET. Refer to the typical
application circuit (see Figure 46) for the required external components.
24
VDET
Detector Voltage for the Power Detector (See Figure 7). VDET is the dc voltage representing the RF
output power rectified by the diode, which is biased through an external resistor. Refer to the typical
application circuit (see Figure 46) for the required external components.
26, 30, 34, 38
VDD4B to
VDD1B
Second Stage Drain Bias Voltage for the Power Amplifier (See Figure 5).
28, 32, 36, 40
VGG4B to
VGG1B
Second Stage Gate Bias Voltage for the Power Amplifier (See Figure 8). For the required external
components, see Figure 46.
Die Bottom
GND
Ground. The die bottom must be connected to the RF/dc ground (see Figure 3).


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