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MCRF250 bảng dữ liệu(PDF) 5 Page - Microchip Technology

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MCRF250 bảng dữ liệu(HTML) 5 Page - Microchip Technology

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 2003 Microchip Technology Inc.
DS21267F-page 5
MCRF250
2.2
Configuration Register and
Control Logic
The configuration register determines the operational
parameters of the device. The configuration register
can
not
be
programmed
contactlessly;
it
is
programmed during wafer probe at the Microchip fac-
tory. CB11 is always a one; CB12 is set when success-
ful contact or contactless programming of the data
array has been completed. Once CB12 is set, device
programming and erasing is disabled. Table 2-1
contains a description of the bit functions of the control
register.
2.2.1
BAUD RATE TIMING OPTION
The chip will access data at a baud rate determined by
bits CB2, CB3, and CB4 of the configuration register.
For example, MOD32 (CB2 = 0, CB3 = 1, CB4 = 1) has
32 RF cycles per bit. This gives the data rate of 4 kHz
for the RF carrier frequency of 128 kHz.
The default timing is MOD 128 (FCLK/128), and this
mode is used for contact and contactless program-
ming. Once the array is successfully programmed, the
lock bit CB12 is set. When the lock bit is set, program-
ming and erasing the device becomes permanently
disabled. The configuration register has no effect on
device timing until the EEPROM data array is
programmed (CB12 = 1).
2.2.2
DATA ENCODING OPTION
This logic acts upon the serial data being read from the
EEPROM. The logic encodes the data according to the
configuration bits CB6 and CB7. CB6 and CB7
determine the data encoding method. The available
choices are:
• Non-return to zero-level (NRZ_L)
• Biphase_S (Differential)
• Biphase_L (Manchester)
• Inverted Manchester
2.2.3
MODULATION OPTION
CB8 and CB9 determine the modulation protocol of the
encoded data. The available choices are:
• ASK
•FSK
• PSK_1
• PSK_2
When ASK (direct) option is chosen, the encoded data
is fed into the modulation transistor without change.
When FSK option is chosen, the encoded data is
represented by:
a)
Sets of 10 RF carrier cycles (first 5 cycles
higher amplitude, the last 5 cycles
→ lower
amplitude) for logic “high” level.
b)
Sets of 8 RF carrier cycles (first 4 cycles
higher amplitude, the last 4 cycles
→ lower
amplitude) for logic “low” level.
For example, FSK signal for MOD40 is represented:
a)
4 sets of 10 RF carrier cycles for data ‘1’.
b)
5 sets of 8 RF carrier cycles for data ‘0’.
Refer to Figure 2-2 for the FSK signal with MOD40
option.
The PSK_1 represents change in the phase of the
modulation signal at the change of the encoded data.
For example, the phase changes when the encoded
data is changed from ‘1’ to ‘0’, or from ‘0’ to ‘1’.
The PSK_2 represents change in the phase at the
change on ‘1’. For example, the phase changes when
the encoded data is changed from ‘0’ to ‘1’, or from ‘1’
to ‘1’.
FIGURE 2-2:
ENCODED DATA AND FSK OUTPUT SIGNAL FOR MOD40 OPTION
Encoded Data ‘1’
Encoded Data ‘0’
40 RF cycles
40 RF cycles
5 cycles (HI)
5 cycles (LO)
4 cycles (HI)
4 cycles (LO)


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