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CA3338E bảng dữ liệu(PDF) 3 Page - Renesas Technology Corp |
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CA3338E bảng dữ liệu(HTML) 3 Page - Renesas Technology Corp |
3 / 10 page CA3338, CA3338A FN1850 Rev 4.00 Page 3 of 10 July 2004 Absolute Maximum Ratings Thermal Information DC Supply-Voltage Range . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V (VDD - VSS or VDD - VEE, Whichever is Greater) Input Voltage Range Digital Inputs (LE, COMP D0 - D7). . . . VSS - 0.5V to VDD + 0.5V Analog Pins (VREF+, VREF-, VOUT) . . . .VDD - 8V to VDD + 0.5V DC Input Current Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . . 20mA Recommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5V Operating Conditions Temperature Range (TA) Plastic Package, E suffix, M suffix . . . . . . . . . . . . . . -40oC to 85oC Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF- = GND, LE Clocked at 20MHz, RL 1 M, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution 8 - - Bits Integral Linearity Error See Figure 4 CA3338 - - 1LSB CA3338A - - 0.75 LSB Differential Linearity Error See Figure 4 CA3338 - - 0.75 LSB CA3338A - - 0.5 LSB Gain Error Input Code = FFHEX, See Figure 3 CA3338 - - 0.75 LSB CA3338A - - 0.5 LSB Offset Error Input Code = 00HEX; See Figure 3 - - 0.25 LSB DIGITAL INPUT TIMING Update Rate To Maintain 1/2 LSB Settling DC 50 - MHz Update Rate VREF- = VEE = -2.5V, VREF+ = +2.5V DC 20 - MHz Set Up Time tSU1 For Low Glitch - -2 - ns Set Up Time tSU2 For Data Store - 8 - ns Hold Time tH For Data Store - 5 - ns Latch Pulse Width tW For Data Store - 5 - ns Latch Pulse Width tW VREF- = VEE = -2.5V, VREF+ = +2.5V - 25 - ns OUTPUT PARAMETERS RL Adjusted for 1VP-P Output Output Delay tD1 From LE Edge - 25 - ns Output Delay tD2 From Data Changing - 22 - ns Rise Time tr 10% to 90% of Output - 4 - ns Settling Time tS 10% to Settling to 1/2 LSB - 20 - ns Output Impedance VREF+ = 6V, VDD = 6V 120 160 200 Glitch Area - 150 - pV/s Glitch Area VREF- = VEE = -2.5V,VREF+ = +2.5V - 250 - pV/s |
Số phần tương tự - CA3338E |
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Mô tả tương tự - CA3338E |
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