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ISL21400IU8Z-TK bảng dữ liệu(PDF) 5 Page - Renesas Technology Corp

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ISL21400IU8Z-TK bảng dữ liệu(HTML) 5 Page - Renesas Technology Corp

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ISL21400
FN8091 Rev 3.00
Page 5 of 17
March 31, 2011
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 2)
MAX
UNITS
ILI
Input Leakage
VIN = GND to VCC
1V
VIL
Input LOW Voltage
-0.3
0.3 x VCC
V
VIH
Input HIGH Voltage
0.7 x VCC
VCC + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VCC
V
VOL
SDA Output Buffer LOW Voltage
IOL = 3mA
0
0.4
V
Cpin
Pin Capacitance
(Note 7)
10
pF
fSCL
SCL Frequency
(Note 7)
400
kHz
tsp
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed
(Note 7)
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
30% of VCC, until SDA exits
the 30% to 70% of VCC
window (Note 7)
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC
during a STOP condition, to
SDA crossing 70% of VCC
during the following START
condition (Note 7)
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC
crossing (Note 7)
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC
crossing (Note 7)
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA
falling edge; both crossing
70% of VCC (Note 7)
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge
crossing 30% of VCC to SCL
falling edge crossing 70% of
VCC (Note 7)
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to
70% of VCC window, to SCL
rising edge crossing 30% of
VCC (Note 7)
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge
crossing 70% of VCC to SDA
entering the 30% to 70% of
VCC window (Note 7)
0ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge
crossing 70% of VCC, to
SDA rising edge crossing
30% of VCC (Note 7)
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to
SCL falling edge; both
crossing 70% of VCC
(Note 7)
1300
ns
tDH
Output Data Hold Time
From SCL falling edge
crossing 30% of VCC, until
SDA enters the 30% to 70%
of VCC window (Note 7)
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VCC
(Note 7)
20 + 0.1 x Cb
250
ns


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