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CA3162E bảng dữ liệu(PDF) 3 Page - Renesas Technology Corp

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Giải thích chi tiết về linh kiện  A/D Converters for 3-Digit Display
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CA3162
FN1080 Rev.3.00
Page 3 of 8
Apr 2002
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (Between Pins 7 and 14) . . . . . . . . . . . . . . .+7V
Input Voltage (Pin 10 or 11 to Ground) . . . . . . . . . . . . . . . . . .
15V
Operating Conditions
Temperature Range
CA3162E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 75oC
Thermal Resistance (Typical, Note 1)
JA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details..
Electrical Specifications TA = 25oC, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4k, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range, V+
4.5
5
5.5
V
Supply Current, I+
100k
 to V+ on Pins 3, 4, 5
-
-
17
mA
Input Impedance, ZI
-
100
-
M
Input Bias Current, IIB
Pins 10 and 11
-
-80
-
nA
Unadjusted Zero Offset
V11-V10 = 0V, Read Decoded Output
-12
-
+12
mV
Unadjusted Gain
V11-V10 = 900mV, Read Decoded Output
846
-
954
mV
Linearity
Notes 1 and 2
-1
-
+1
Count
Conversion Rate
Slow Mode
Pin 6 = Open or GND
-
4
-
Hz
Fast Mode
Pin 6 = 5V
-
96
-
Hz
Conversion Control Voltage (Hold Mode)
at Pin 6
0.8
1.2
1.6
V
Common Mode Input Voltage Range, VICR
Notes 3, 4
-0.2
-
+0.2
V
BCD Sink Current at Pins 1, 2, 15, 16
VBCD  0.5V, at Logic Zero State
0.4
1.6
-
mA
Digit Select Sink Current at Pins 3, 4, 5
VDIGIT Select = 4V at Logic Zero State
1.6
2.5
-
mA
Zero Temperature Coefficient
VI = 0V, Zero Pot Centered
-
10
-
V/oV
Gain Temperature Coefficient
VI = 900mV, Gain Pot = 2.4k
-
0.005
-
%/oC
NOTES:
1. Apply 0V across V11 to V10. Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to give
900mV reading.
2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include
0.5 count bit digitizing
error.
3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100k
 resistance must be provided for
input bias currents.
4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is, pin 11
may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input signal is less
than 999mV, the common mode input voltage may be raised accordingly.


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