MC10EP446, MC100EP446

http://onsemi.com

3

Table 2. TRUTH TABLE

Function

Pin

HIGH

LOW

CKSEL

CLK

CLK

CKEN

Synchronously Disables Normal Parallel to Serial Con-

version

Synchronously Enables Normal Parallel to Serial Conversion

SYNC

Asynchronously Resets Internal Flip−Flops*

Synchronous Enable

*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates

the conversion process synchronously on the next rising edge of CLK.

Table 3. INPUT VOLTAGE LEVEL SELECTION TABLE

Input Function

ECL Mode

CMOS Mode

No Connect

TTL Mode*

1.5 V

$ 100 mV

*For TTL Mode, if no external voltage can be provided, the reference

voltage can be provided by connecting the appropriate resistor

Table 4. DATA INPUT OPERATING VOLTAGE TABLE

Power Supply

Data Inputs (D [0:7])

Power Supply

CMOS

TTL

PECL

NECL

PECL

p

p

p

N/A

NECL

N/A

N/A

N/A

p

Power Supply

Resistor Value 10% (Tolerance)

3.3 V

1.5 k

W

5.0 V

500

W