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LM9801CCVF bảng dữ liệu(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện LM9801CCVF
Giải thích chi tiết về linh kiện  Greyscale/24-Bit Color Linear CCD Sensor Processor
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LM9801CCVF bảng dữ liệu(HTML) 8 Page - National Semiconductor (TI)

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Pin Descriptions
CCD Driver Signals
w
1
Digital Output CCD clock signal phase 1
w
2
Digital Output CCD clock signal phase 2
RS
Digital Output Reset pulse for the CCD
TR
Digital Output Transfer pulse for the CCD
Analog IO
OS
Analog Input This is the OS (Output
Signal) from the CCD The maximum peak
signal that can be accurately digitized is
equal to the voltage at REF IN typically
1225V
REF IN
Analog Inputs These two pins are the
system reference voltage inputs and
should be tied together to a 1225V voltage
source and bypassed to AGND with a 01
m
F monolithic capacitor
REF OUTHI
Analog Output This reference voltage is
developed internally by the LM9801 and is
equal to 3 times REF IN It should be
bypassed to AGND with a 01 mF
monolithic capacitor
REF OUTMID Analog Output This reference voltage is
developed internally by the LM9801 and is
equal to 2 times REF IN It should be
bypassed to AGND using a 01 mF
monolithic capacitor
VTEST1
Analog InputsOutputs These pins are
used for testing the device during
VTEST2
manufacture and should be left
unconnected
General Digital IO
MCLK
Digital Input This is the 20 MHz (typical)
master system clock
SYNC
Digital Input A low-to-high transition on this
input begins a line scan operation The line
scan operation terminates when this input
is taken low
Configuration Register IO
SDI
Digital Input Serial Data Input pin
SDO
Digital Output Serial Data Output pin
SCLK
Digital Input This is the serial data clock
used to clock data in through SDI and out
through SDO SCLK is asynchronous to
MCLK Input data is latched and output
data is changed on the rising edge of
SCLK
CS
Digital Input This is the Chip Select signal
for writing to the Configuration Register
through the serial interface This input must
be low in order to communicate with the
Configuration Register This pin is used for
serial IO only – it has no effect on any
other section of the chip
Digital Coefficient IO
CD0 (LSB) –
Digital Inputs Correction Coefficient
Databus This is the 8-bit data path for the
CD7 (MSB)
gain adjust PGA used during line scan
CCLK
Digital Output This is the signal that is used
to clock the Gain coefficients into the
LM9801 Data is latched on the rising edge
of CCLK
Digital Output IO
DD0 (LSB) –
Digital Outputs Pixel Output Databus This
data bus outputs the 8-bit digital output data
DD7 (MSB)
during line scan
EOC
Digital Output This is the End of Conversion
signal from the ADC indicating that new
pixel data is available
RD
Digital Input Taking this input low places
the data stored in the output latch on the
bus When this input is high the DD0 – DD7
bus is in TRI-STATE
Analog Power
VA
This is the positive supply pin for the analog
supply It should be connected to a voltage
source of a5V and bypassed to AGND with
a 01 mF monolithic capacitor in parallel with
a10 mF tantalum capacitor
AGND
This is the ground return for the analog
supply
Digital Power
VD
This is the positive supply pin for the digital
supply It should be connected to a voltage
source of a5V and bypassed to DGND with
a 01 mF monolithic capacitor
DGND
This is the ground return for the digital
supply
VD(IO)
This is the positive supply pin for the digital
supply for the LM9801’s IO It should be
connected to a voltage source of a3V to
a
5V and bypassed to DGND(IO) with a
01 mF monolithic capacitor If the supply for
this pin is different than the supply for VA
and VD it should also be bypassed with a
10 mF tantalum capacitor
DGND(IO)
This is the ground return for the digital
supply for the LM9801’s IO
NC
NC
All pins marked NC (no connect) should be
left floating Do not tie NC pins to ground
power supplies or any other potential or
signal
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