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LM9801CCVF bảng dữ liệu(PDF) 6 Page - National Semiconductor (TI) |
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LM9801CCVF bảng dữ liệu(HTML) 6 Page - National Semiconductor (TI) |
6 / 34 page AC Electrical Characteristics MCLK Independent (Continued) The following specifications apply for AGND e DGND e DGND(IO) e 0V VA e VD e VD(IO) ea50VDC REF IN e a 1225VDC fMCLK e 20 MHz tMCLK e 1fMCLK tr e tf e 5 ns Rs e 25X CL (databus loading) e 50 pFpin Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 7 and 8) Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) tS1H tS0H Delay from CS Rising Edge to SDO RL e 3k CL e 50 pF 25 50 ns (max) TRI-STATE tRDO SDO Rise Time TRI-STATE to High RL e 3k CL e 50 pF 20 ns SDO Rise Time Low to High 20 ns tFDO SDO Fall Time TRI-STATE to Low RL e 3k CL e 50 pF 20 ns SDO Fall Time High to Low 20 ns AC Electrical Characteristics MCLK Dependent The following specifications apply for AGND e DGND e DGND(IO) e 0V VA e VD e VD(IO) ea50VDC REF IN e a 1225VDC fMCLK e 20 MHz tMCLK e 1fMCLK tr e tf e 5 ns Rs e 25X CL (databus loading) e 50 pFpin Refer to Table 2 Configuration Register Parameters for limits labelled CR Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 7 and 8) Symbol Parameter Conditions Typical Limits Units (Note 9) (Note 10) (Limits) tSTART MCLK to first w1 High 50 ns 1 tMCLK tw w 1 w2 Clock Period Standard CCD Mode 400 ns 8 tMCLK EvenOdd CCD Mode 800 ns 16 tMCLK tTRWIDTH Transfer Pulse (TR) Width CR m s tGUARD w 1 to TR TR to w1 Guardband CR ns tRSWIDTH Reset Pulse (RS) Width CR ns tRS Falling Edge of w1 to RS Standard CCD Mode CR ns Either Edge of w1 to RS EvenOdd CCD Mode tSHREF Falling Edge of w1 to Ref Sample Standard CCD Mode CR ns Either Edge of w1 to Ref Sample EvenOdd CCD Mode tSHSIG Falling Edge of w1 to Sig Sample Standard CCD Mode CR ns Either Edge of w1 to Sig Sample EvenOdd CCD Mode tSHWIDTH Sample Pulse Width 50 ns 1 tMCLK (Acquisition Time) tSYNCLOW SYNC Low Between Lines 100 ns 2 tMCLK (min) tB SYNC Setup of w1 to End Line 2 tMCLK (max) tCCLKWIDTH CCLK Pulse Width 250 ns 5 tMCLK tDATAVALID Data Valid Time from EOC Low 300 ns (min) tEOCWIDTH EOC Pulse Width 250 ns 5 tMCLK w 1 and w2 Frequency Standard CCD Mode 25 MHz fMCLK 8 Hz EvenOdd CCD Mode 125 MHz fMCLK 16 Hz w 1 and w2 Duty Cycle 50 % http www nationalcom 6 |
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