KM29U64000T, KM29U64000IT

FLASH MEMORY

7

MODE SELECTION

2. WP should be biased to CMOS high or CMOS low for standby.

3. When SE is high, spare area is deselected.

CLE

ALE

CE

WE

RE

SE

WP

Mode

H

L

L

H

X

X

Read Mode

Command Input

L

H

L

H

X

X

Address Input(3clock)

H

L

L

H

X

H

Write Mode

Command Input

L

H

L

H

X

H

Address Input(3clock)

L

L

L

H

H

Data Input

L

L

L

H

X

Sequential Read & Data Output

L

L

L

H

H

X

During Read(Busy)

X

X

X

X

X

H

During Program(Busy)

X

X

X

X

X

X

H

During Erase(Busy)

X

X

X

X

X

L

Write Protect

X

X

H

X

X

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

-

10

pF

Input Capacitance

-

10

pF

VALID BLOCK

NOTE :

1. The KM29U64000 may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid

blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaran-

teed though its initial number could be reduced. (Refer to the attached technical notes)

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

1014

1020

1024

Blocks

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

-

200

1000

µs

Number of Partial Program Cycles in the Same Page

Nop

-

-

10

cycles

Block Erase Time

-

2

4

ms

AC TEST CONDITION

Parameter

Value

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Times

5ns

Input and Output Timing Levels

0.8V and 2.0V

Output Load (3.0V +/-10%)

1 TTL GATE and CL = 50pF

Output Load (3.3V +/-10%)

1 TTL GATE and CL = 100pF