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LMZM23601SILT bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LMZM23601SILT bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 44 page 7 LMZM23601 www.ti.com SNVSAQ4A – DECEMBER 2017 – REVISED APRIL 2018 Product Folder Links: LMZM23601 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD FLAG (PGOOD) VPGOOD_OV PGOOD upper threshold voltage Rising, % of Vout 103.5% 106.7% 109% VPGOOD_UV PGOOD lower threshold voltage Falling, % of Vout 92% 94.7% 97% VPGOOD_GUARD Magnitude of PGOOD lower threshold difference from steady state output voltage. Steady state output voltage PGOOD threshold read at the same TJ and VIN 4% VPGOOD_HYST PGOOD hysteresis as a percent of output voltage set point 1.4% VPGOOD_VALID Minimum input voltage for proper PGOOD function 50-µA pullup to PGOOD pin, EN = 0 V, TJ = 25°C 1.0 1.5 V tRESET_FILTER Glitch filter time constant for PGOOD function 190 µs VOL Low-level PGOOD function output voltage 50-µA pullup to PGOOD pin, VIN = 1.5 V, EN = 0 V 0.4 V 0.5-mA pullup to PGOOD pin, VIN = 12 V, EN = 0 V 0.4 1-mA pullup to PGOOD pin, VIN = 12 V, EN = 3.3 V 0.4 RPGOOD_RDSON RDSON of the PGOOD output pull down 50 110 Ω SWITCHING FREQUENCY fSW Switching frequency VIN = 24 V, 5-V and 3.3-V fixed output options 675 750 825 kHz VIN = 24 V, ADJ output options 890 1000 1090 VIN = 36 V, 5-V and 3.3-V fixed output options 750 VIN = 36 V, ADJ output options 800 FREQUENCY SYNCHRONIZATION AND MODE fSYNC Sync frequency range 5-V and 3.3-V fixed output options VOUT + VDROPOUT < VIN < 36 V 500 825 kHz ADJ output options VOUT + VDROPOUT< VIN < 28 V 700 1100 DSYNC Sync input duty cycle range 2.3 V < HIGH state input < 5.5 V 25% 75% VMODE_HIGH MODE/SYNC input logic HIGH voltage to enter FPWM mode 1.5 V VMODE_LOW MODE/SYNC input logic LOW voltage to enter AUTO PFM mode 0.4 V IMODE MODE/SYNC leakage current VIN = 12 V, VMODE/SYNC = 3.3 V 1 µA VIN = 12 V, VMODE/SYNC = 12V 5 tMODE MODE transition time to FPWM VIN = 12 V, VOUT = 5 V, IOUT= 20 mA 300 µs MODE transition time to AUTO PFM VIN = 12 V, VOUT = 5 V, IOUT = 20 mA 300 CURRENT LIMIT PROTECTION IL-HS high-side switch current limit Duty cycle approaches 0% 1.45 1.81 2.2 A IL-LS low-side switch current limit 1 1.2 1.43 A IL-ZC Zero-cross current limit MODE/SYNC = logic LOW –0.01 A IL-NEG Low-side reverse current limit (positive current ino the SW pin to GND) MODE/SYNC = logic HIGH 0.5 0.8 A |
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