SM3473A/B

SEIKO NPC CORPORATION - 7

The interpolation circuit converts the analog input signal amplified by the amplifier circuit to binary using a resistor voltage divider

comparator, and outputs 2-phase digital signals using logic signal processing. The comparator has a hysteresis of approximately

45mV.

The interpolation factor is determined by the High/Low voltage combination applied to the IPSL0 and IPSL1 pins.

The interpolation factor settings are shown in the following table.

Ver.A

Ver. B

IPSL1

IPSL0

Interpolation

factor

IPSL1

IPSL0

Interpolation

factor

0

0

8

0

0

16

0

1

4

0

1

8

1

0

2

1

0

4

1

1

1

1

1

2

The MODE pins are used to switch the internal node of the device for monitoring signals, and to switch to power-down mode.

The output on the output pins (DA, DB, EX1, EX2) are controlled by the High/Low combination on the MODE pins.

The mode switching settings are shown in the following table.

MODE2

MODE1

MODE0

Operating mode

DA

DB

EX1

EX2

0

0

0

Normal operating mode (digital output)

dig_A

dig_B

Hi-Z

Hi-Z

0

0

1

EX_OR output ON

dig_A

dig_B

exor(da,db)

Hi-Z

0

1

0

Output tied "L"

L

L

Hi-Z

Hi-Z

0

1

1

Output tied "H"

H

H

Hi-Z

Hi-Z

1

0

0

Simultaneous analog output mode

(Non-inverted output)

dig_A

dig_B

ana_A

ana_B

1

0

1

Analog output mode

(Inverted / Non-inverted output)

ana_AN

ana_BN

ana_A

ana_B

1

1

0

Power-down mode

Hi-Z

Hi-Z

Hi-Z

Hi-Z

1

1

1

In the table, dig_A/dig_B indicates the interpolation output, and ana_A/ana_AN/ana_B/ana_BN indicate the analog signal outputs

after signal amplification.

The analog output mode is used to check the analog waveform after internal amplification. It can be used for debugging during

prototyping, for example.

In power-down mode, the internal circuits stop and the current consumption falls below 1µA. Power-down mode is selected by

setting MODE2 and MODE1 to the same potential as VDD; the state of MODE0 has no effect.