AD5247BKS50-R2 datasheet(5/20 Pages) AD

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AD5247

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

I2C INTERFACE TIMING CHARACTERISTICS2, 3

(Specifications Apply to All Parts)

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus Free Time between STOP and START

t1

1.3

µs

tHD;STA Hold Time (Repeated START)

t2

After this period, the first clock pulse is

generated.

0.6

µs

tLOW Low Period of SCL Clock

t3

1.3

µs

tHIGH High Period of SCL Clock

t4

0.6

50

µs

tSU;STA Setup Time for Repeated START Condition

t5

0.6

µs

tHD;DAT Data Hold Time

t6

0.9

µs

tSU;DAT Data Setup Time

t7

100

ns

tF Fall Time of Both SDA and SCL Signals

t8

300

ns

tR Rise Time of Both SDA and SCL Signals

t9

300

ns

tSU;STO Setup Time for STOP Condition

t10

0.6

µs

1 Typical specifications represent average readings at 25°C and VDD = 5 V.

2 Guaranteed by design and not subject to production test.

3 See timing diagrams (

, Figu

,

) for locations of measured values.

Figure 31

re 32 Figure 33

Rev. 0 | Page 5 of 20

Số phần tương tự - AD5247BKS50-R2

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Analog Devices	AD5247BKSZ10-1RL7	489Kb / 20P	128-Position I2C-Compatible Digital Potentiometer Rev. F
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Mô tả tương tự - AD5247BKS50-R2

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