No. 6302-6/7

LC35256FM, FT-55U/70U

Notes:1. WE must be held at the high level during the read cycle.

first.

level.

6. The OE pin must be either held high or held low during the write cycle.

Parameter

Symbol

Conditions

min

typ*

max

Unit

Data retention supply voltage

2.0

5.5

V

Ta

≤ 25°C

0.02

Data retention supply current

Ta

≤ 60°C

1.0

µA

Ta

≤ 70°C

2.0

Ta

≤ 85°C

3.5

Chip enable setup time

0ns

Chip enable hold time

ns

Data Retention Conditions at Ta = –40 to +85°C

Data Retention Waveforms

VCC

VCCL*

VIH

VDR

VCE

GND

VCE ≥ VCC – 0.2 V

tCDR

tR

Data retention mode

Circuit Design Notes

When designing application circuits, always take the following into consideration and design the circuits so that the

absolute maximum ratings are never exceeded.

• Supply voltage fluctuations

• Sample-to-sample variations in the electrical characteristics of the electronic components used, including

semiconductor devices, resistors, and capacitors.

• Ambient temperature

• Variations in the input and clock signals

• The application of abnormal pulses

Furthermore, be sure to operate this device within the stipulated ranges of all parameters for which an allowable

operating range is specified.

When CMOS IC input pins are left in the open state, through currents may occur in internal circuits to which

intermediate voltage levels are applied, and this can result in incorrect circuit operation. Be sure to handle all unused

input pins as specified in the device documentation.