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GS7000 bảng dữ liệu(PDF) 2 Page - List of Unclassifed Manufacturers |
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GS7000 bảng dữ liệu(HTML) 2 Page - List of Unclassifed Manufacturers |
2 / 14 page 522 - 06 - 02 2 ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage 5.5V Input Voltage Range (any input) VEE < VIN < VCC DC Input Current (any one input) 10mA Power Dissipation (VCC = 5.25 V) 830mW Maximum Die Temperature 125°C Operating Temperature Range 0°C ≤ TA ≤ 85°C Storage Temperature Range -65°C ≤ TS ≤ 150°C Lead Temperature (soldering 10s) 260°C AC ELECTRICAL CHARACTERISTICS (Receiver Mode) VCC = 5V, VEE = 0V, TA = 0°C to 85°C, unless otherwise specified. Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, fPCLK = 27MHz PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES TEST LEVEL Parallel Data Output - Rise/Fall Time CL = 20pF tR/F_PDO 1.0 - 6.0 ns 1 1 PCLK rising edge to DOUT(n) center tD -- ± 5 ns 2, 3 1 PCLK rise/fall time CL = 20pF tR/F_PCLKo 0.5 - 3.0 ns 1 1 Input Return Loss 75 Ω match 5MHz -> 270MHz LOSSIN -17 - dB 6 Asynchronous Lock Time tLOCK_ASYNC - - 250 ms 4 1 Synchronous Lock Time tLOCK_SYNC - - 10 µs 5 1 Input Jitter Tolerance pathological Input tJ_SI -0.4 - U.I. 6 4 Output PCLK Jitter pathological Input tJ_PCLKo - 1000 - ps p-p 6 1 Max Error Free Cable Length pathological Input 75 100 - m 6, 7 1, 4 NOTES 1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the specified value. 2. Refer also to Figure 21. 3. This is the time difference between the rising edge of PCLKOUT and the center of the bit period. 4. This is the time delay between a valid serial TRS signal on the input, to the moment valid data appears on the parallel outputs. 5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE RP168-1993. The two streams may be 180° out of phase with respect to one another, but pixel aligned. 6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3. 7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75 Ω connections. The MIN value is fully tested and the TYP value is based on using the EB7000 Evaluation Board. TEST LEVELS 1. 100% tested at 25 °C 2. Guaranteed by design 3. Inferred or correlated value 4. Evaluated using test setup Figure 1a. 5. Evaluated using test setup Figure 1b. 6. Evaluated using test setup Figure 1c. |
Số phần tương tự - GS7000 |
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Mô tả tương tự - GS7000 |
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