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MCP6S21 bảng dữ liệu(PDF) 4 Page - Microchip Technology

tên linh kiện MCP6S21
Giải thích chi tiết về linh kiện  Single-Ended, Rail-to-Rail I/O, Low Gain PGA
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MCP6S21 bảng dữ liệu(HTML) 4 Page - Microchip Technology

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MCP6S21/2/6/8
DS21117A-page 4
 2003 Microchip Technology Inc.
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA =+25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL =10 kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
VIL
0
0.3VDD
V
Input Leakage Current
IIL
-1.0
+1.0
µA
Logic Threshold, High
VIH
0.7VDD
—VDD
V
Amplifier Output Leakage Current
-1.0
+1.0
µA
In Shutdown mode
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low
VOL
VSS
—VSS+0.4
V
IOL = 2.1 mA, VDD = 5V
Logic Threshold, High
VOH
VDD-0.5
VDD
VIOH = -400 µA
SPI Timing
Pin Capacitance
CPIN
10
pF
All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK)
tRFI
——
2
µs
Note 1
Output Rise/Fall Times (SO)
tRFO
5
ns
MCP6S26 and MCP6S28
CS high time
tCSH
40
ns
SCK edge to CS fall setup time
tCS0
10
ns
SCK edge when CS is high
CS fall to first SCK edge setup time
tCSSC
40
ns
SCK Frequency
fSCK
——
10
MHz
VDD = 5V (Note 2)
SCK high time
tHI
40
ns
SCK low time
tLO
40
ns
SCK last edge to CS rise setup time
tSCCS
30
ns
CS rise to SCK edge setup time
tCS1
100
ns
SCK edge when CS is high
SI set-up time
tSU
40
ns
SI hold time
tHD
10
ns
SCK to SO valid propagation delay
tDO
80
ns
MCP6S26 and MCP6S28
CS rise to SO forced to zero
tSOZ
80
ns
MCP6S26 and MCP6S28
Channel and Gain Select Timing
Channel Select Time
tCH
1.5
µs
CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS = 0.7VDD to VOUT 90% point
Gain Select Time
tG
1
µs
CHx = 0.3V, G = 5 to G = 1 select,
CS = 0.7VDD to VOUT 90% point
Shutdown Mode Timing
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
tON
—3.5
10
µs
CS = 0.7VDD to VOUT 90% point
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
Time
tOFF
—1.5
µs
CS = 0.7VDD to VOUT 90% point
POR Timing
Power-On Reset power-up time
tRPU
—30
µs
VDD = VPOR - 0.1V to VPOR + 0.1V,
50% VDD to 90% VOUT point
Power-On Reset power-down time
tRPD
—10
µs
VDD = VPOR + 0.1V to VPOR - 0.1V,
50% VDD to 90% VOUT point
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (tDO ≤ 80 ns), data input setup time (tSU ≥ 40 ns), SCK high time (tHI ≥ 40 ns), and SCK rise and
fall times of 5 ns. Maximum fSCK is, therefore, ≈ 5.8 MHz.


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