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ML145428 bảng dữ liệu(PDF) 8 Page - LANSDALE Semiconductor Inc. |
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ML145428 bảng dữ liệu(HTML) 8 Page - LANSDALE Semiconductor Inc. |
8 / 14 page www.lansdale.com Page 8 of 14 Issue 0 LANSDALE Semiconductor, Inc. ML145428 receiver section of the DSI is forced into a “HOLD” state while the RESET line is low. The synchronous channel receiv- er remains in the “HOLD” state after RESET goes high until a flag code word (01111110) is received at the DCI pin. While in the “HOLD” state no data words can be transferred to the Rx FIFO and, therefore, the DATA FORMATTER and RxD line are hold in the MARK idle state. After receiving the flag code pattern the RxS line goes high and normal operation proceeds. RESET should be held low when power is first applied to the DSI. RESET may be tied high permanently, if a short period of undefined operation at initial power application can be tolerat- ed. SYNCHRONOUS CHANNEL INTERFACE The synchronous channel interface is generally operated in one of three basic modes of operation. The first is a continuous mode. A new data bit is clocked out of the DCO pin on each successive falling edge of the DC clock, and a new data bit is accepted by the DSI at its DCI pin on each successive falling edge of the DC clock. In this mode of operation, the CM con- trol line is always low and the DOE and DIE enable control lines are always High. This is the typical setup when interfac- ing the DSI to the 8 kbps signal bit inputs and outputs of the MC145422/26 UDLTs (See Figures 3A and 4) The second synchronous clocking mode is one in which 8 bits at a time are clocked out at the SYNCHRONOUS CHAN- NEL TRANSMITTER, and 8 bits are read by the SYNCHRO- NOUS CHANNEL RECEIVER at a time. The transferring of these 8 bit groups of data would normally be repeated on some cyclic basis. An example is a time division multiplexed data highway. In this mode (Cm = 1), the rising edge of the enable signal DIE and DOE should be roughly aligned to the rising edge of the DC clock signal. When enabled, the data is clocked out on the rising edge of the DC clock through the DCO pin and clocked in on the falling edge of the DC clock through the DCI pin. A variation of this clocking mode is to transfer less than 8 bits of data into or out of the DSI on a cyclic basis. If less than eight bits are to be transmitted and received, enable pins DIE and DOE should be returned low while the DC clock is low. This is illustrated in Figure 3D where five bits are being locked out of the DSI through the DCO pin and four bits are being input to the DSI through the DCI pin. This restriction does not apply if eight bits are to be clocked into or out of the synchronous channels of the DSI, i.e., the DSI has internal circuitry to prevent more than eight clocks following the rising edge of the respective enable signal(s). Figure 3B illustrates a timing diagram depicting an eight bit data format. If the DOE enable is held high beyond the eight clock periods the last data bit B8 will remain at the output of the DCO pin until the DOE enable is brought low to reinitial- ize the sequence. Similarly the DSI’s SYNCHRONOUS CHANNEL RECEIVER will read (at its DCI input) a mini- mum of eight data bits for any given DIE high period. The CM = high mode, using 8 bits of data, is the typical set up for interfacing the DSI to the 64 kbps channel of the MC145422 or MC145426 Universal Digital Loop Transceivers. (See Figure 3B and Figure 5). In the third mode of operation, an unlimited variable number of data bits may be clocked into or out of the synchronous side of the DSI at a time. When the CM line is low, any number of data bits may be clocked into or out of the DSI’s synchronous channels provided that the respective enable signal is high. Figure 3C illustrates three data bits being clocked out of the DCO pin and three data bits being clocked into the DCI pin. In the CM = low mode of operation, an internal clock is formed, which is the logical NAND of DC, DOE and CM, (IDC•DOE•CM). It is on the rising edge of this signal that a new data bit is clocked out of the DCO pin. Therefore, the DOE signal should be raised and lowered following the falling edge of the DC clock (i.e., when the DC clock is low). Also in the CM = low mode of operation another internal clock is formed which is the logical NAND of DC, DIE, and CM (DC•DIE•CM). It is on the falling edge of this signal that a new bit is clocked into the DCI pin. Therefore the DIE signal should be raised or lowered following the rising edge of the DC clock (i.e., when the DC clock is high). The following table summarizes when data bits are advanced from the synchronous channel transmitter and when data bits are read by the synchronous channel receiver dependent on the CM control line. (Shown below in Table 2.) |
Số phần tương tự - ML145428_08 |
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Mô tả tương tự - ML145428_08 |
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