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MC145051P bảng dữ liệu(PDF) 11 Page - LANSDALE Semiconductor Inc. |
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MC145051P bảng dữ liệu(HTML) 11 Page - LANSDALE Semiconductor Inc. |
11 / 15 page www.lansdale.com Page 11 of 15 LANSDALE Semiconductor, Inc. ML145050, ML145051 DESCRIPTION This example application of the ML145050/ML145051 ADCs interfaces three controllers to a microprocessor and processes data in real-time for a video game. The standard joy- stick X-axis (left/right) and Y-axis (up/down) controls as well as engine thrust controls are accommodated. Figure 15 illustrates how the ML145050/ML145051 is used as a cost-effective means to simplify this type of circuit design. Utilizing one ADC, three controllers are interfaced to a CMOS or NMOS microprocessor with a serial peripheral interface (SPI) port. Processors with National Semiconductor's MICROWIRE serial port may also be used. Full duplex opera- tion optimizes throughput for this system. DIGITAL DESIGN CONSIDERATIONS Motorola's MC68HC05C4 CMOS MCU may be chosen to reduce power supply size and cost. The NMOS MCUs maybe used if power consumption is not critical. A VDD or VSS 0.1 µF bypass capacitor should be closely mounted to the ADC. Both the ML145050 and ML145051 accommodate all the analog system inputs. The ML145050, when used with a 2 MHz MCU, takes 27 µs to sample the analog input, perform the conversion, and transfer the serial data at 2 MHz. Forty- four ADCLK cycles (2 MHz at input pin 19) must be provided and counted by the MCU before reading the ADC results. The ML145051 has the end-of-conversion (EOC) signal (at output pin 19) to define when data is ready, but has a slower 49 µs cycle time. However, the 49 µs is constant for serial data rates of 2 MHz independent of the MCU clock frequency. Therefore, the ML145051 may be used with the CMOS MCU operating at reduced clock rates to minimize power consumption without severely sacrificing ADC cycle times, with EOC being used to generate an interrupt. (The ML145051 may also be used with MCUs which do not provide a system clock.) ANALOG DESIGN CONSIDERATIONS Controllers with output impedances of less than 1 k Ω maybe directly interfaced to these ADCs, eliminating the need for buffer amplifiers. Separate lines connect the Vref and VAG pins on the ADC with the controllers to provide isolation from system noise. Although not indicated in Figure 15, the Vref and controller output lines may need to be shielded, depending on their length and electrical environment. This should be verified during pro- totyping with an oscilloscope. If shielding is required, a twist- ed pair or foil-shielded wire (not coax) is appropriate for this low frequency application. One wire of the pair or the shield must be VAG. A reference circuit voltage of 5 volts is used for this applica- tion. The reference circuitry may be as simple as tying VAG to system ground and Vref to the system's positive supply. (See Figure 16.) However, the system power supply noise may require that a separate supply be used for the voltage reference. This supply must provide source current forVref as well as current for the controller potentiometers. A bypass capacitor of approximately 0.22 µF across the Vref and VAG pins is recommended. These pins are adjacent on the ADC package which facilitates mounting the capacitor very close to the ADC. SOFTWARE CONSIDERATIONS The software flow for acquisition is straight forward. The nine analog inputs, AN0 through AN8, are scanned by reading the analog value of the previously addressed channel into the MCU and sending the address of the next channel to be read to the ADC, simultaneously. If the design is realized using the ML145050, 44 ADCLK cycles (at pin 19) must be counted by the MCU to allow time for A/D conversion. The designer utilizing the MC145051 has the end-of-conversion signal (at pin 19) to define the conver- sion interval. EOC may be used to generate an interrupt, which is serviced by reading the serial data from the ADC. The soft- ware flow should then process and format the data, and transfer the information to the video circuitry for updating the display. When these ADCs are used with a 16-bit (2-byte) transfer, there are two types of offsets involved. In the first type of off- set, the channel information sent to the ADCs is offset by 12 bits. That is, in the 16-bit stream, only the first 4 bits (4 MSBs) contain the channel information. The balance of the bits are don't cares. This results in 3 don't-care nibbles, as shown in Table 2. The second type of offset is in the conversion result returned from the ADCs; this is offset by 6 bits. In the 16-bit stream, the first 10 bits (10 MSBs) contain the conversion results. The last 6 bits are zeroes. The hexadecimal result is shown in the first column of Table 3. The second column shows the result after the offset is removed by a microprocessor rou- tine. If the 16-bit format is used, these ADCs can transfer one continuous 16-bit stream or two intermittent 8-bitstreams. Legacy Applications Information Issue B |
Số phần tương tự - MC145051P |
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Mô tả tương tự - MC145051P |
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