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ML145162EP bảng dữ liệu(PDF) 8 Page - LANSDALE Semiconductor Inc. |
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ML145162EP bảng dữ liệu(HTML) 8 Page - LANSDALE Semiconductor Inc. |
8 / 24 page www.lansdale.com Page 8 of 24 Issue 0 LANSDALE Semiconductor, Inc. ML145162 Figure 8. Programming Format of the Control Register NOTE: ENB must be high during the serial transfer. ENB CONTROL REGISTER IDENTIFIER = 1 REF PD ENABLE RxPD ENABLE TxPD ENABLE 10 TEST BIT AUX DATA SELECT CONTROL REGISTER DATA Din REF OUT MSB LSB CLK 3/ 4 Table 1. Control Register Function Bits Description Test Bit Set to 1 for Tx/Rx channel counter test mode Set to 0 for normal application Aux Data Select Set to 1 for both ADin and Din pins inputting the transmit 16–bits data and receive 16–bits data respectively. Set to 0 for normal application interfacing with MCU serial peripheral interface. Does not use ADin pin; tie ADin to VSS. REFout 3/ 4 If set to 1, REFout output frequency is equal to OSCout 3. If set to 0, REFout output is OSCout 4. TxPD Enable If set to 1, the transmit counter, transmit phase detector, and the associated circuitry is in power– down mode. Tx PS/fTx is set “High”. RxPD Enable If set to 1, the receive counter, receive phase detector, and the associated circuitry is in power– down mode. Rx PS/fRx is set “High”. Ref PD Enable If set to 1, both 12–bit and 14–bit reference frequency counters are in power–down mode. Table 2. Control Register Power Down Bits Function TxPD Enable RxPD Enable REF PD Enable Tx–Channel Counter Rx–Channel Counter Reference Frequency Counter 0 0 0 — — — 0 0 1 — — Power Down 0 1 0 — Power Down — 0 1 1 — Power Down Power Down 1 0 0 Power Down — — 1 0 1 Power Down — Power Down 1 1 0 Power Down Power Down — 1 1 1 Power Down Power Down Power Down |
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