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MC145053D bảng dữ liệu(PDF) 6 Page - LANSDALE Semiconductor Inc.

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Issue A
ML145053
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
DIGITAL INPUTS AND OUTPUT
The various serial bit-stream formats for the ML145053 are
illustrated in the timing diagrams of Figures 9 through 14.
Table 1 assists in selection of the appropriate diagram. Note
that the ADC accepts 16 clocks which makes it SPI (Serial
Peripheral Interface) compatible.
CS
Active-Low Chip Select Input (Pin 10)
Chip select initializes the chip to perform conversions and
provides 3-state control of the data output pin (Dout). While
inactive high, CS forces Dout to the high-impedance state and
disables the data input (Din) and serial clock (SCLK) pins. A
high-to-low transition on CS resets the serial dataport and syn-
chronizes it to the MPU data stream. CS can remain active
during the conversion cycle and can stay in the active low state
for multiple serial transfers or CS can be inactive high after
each transfer. If CS is kept active low between transfers, the
length of each transfer is limited to either 10 or 16 SCLK
cycles. If CS is in the inactive high state between transfers,
each transfer can be anywhere from 10 to16 SCLK cycles
long. See the SCLK pin description for a more detailed discus-
sion of these requirements.
Spurious chip selects caused by system noise are minimized
by the internal circuitry. Any transitions on the CS pin are rec-
ognized as valid only if the level is maintained for about 2 µs
after the transition.
NOTE
If CS is inactive high after the 10th SCLK cycle and
then goes active low before the A/D conversion is com-
plete, the conversion is aborted and the chip enters the
initial state, ready for another serial transfer/conversion
sequence. At this point, the output data register contains
the result from the conversion before the aborted con-
version. Note that the last step of the A/D conversion
sequence is to update the output data register with the
result. Therefore, if CS goes active low in an attempt to
abort the conversion too close to the end of the conver-
sion sequence, the result register may be corrupted and
the chip could be thrown out of sync with the processor
until CS is toggled again (refer to the AC Electrical
Characteristics in the spec tables).
Dout
Serial Data Output of the A/D Conversion Result (Pin 11)
This output is in the high-impedance state when CS is in-
active high. When the chip recognizes a valid active low on
CS, Dout is taken out of the high-impedance state and is driv-
en with the MSB of the previous conversion result. (For the
first transfer after power-up, data on Dout is undefined for the
entire transfer.) The value on Dout changes to the second most
significant result bit upon the first falling edge of SCLK.The
remaining result bits are shifted out in order, with the LSB
appearing on Dout upon the ninth falling edge of SCLK. Note
that the order of the transfer is MSB to LSB. Upon the10th
falling edge of SCLK, Dout is immediately driven low (if
allowed by CS) so that transfers of more than 10 SCLKs read
zeroes as the unused LSBs.
When CS is held active low between transfers, Dout is driv-
en from a low level to the MSB of the conversion result for
three cases: Case 1 – upon the 16th SCLK falling edge if the
transfer is longer than the conversion time (Figure 14); Case 2
– upon completion of a conversion for a 16-bit transfer interval
shorter than the conversion (Figure 12); Case 3 – upon com-
pletion of a conversion for a 10-bit transfer (Figure 10).
Din
Serial Data Input (Pin 12)
The four-bit serial input stream begins with the MSB of the
analog mux address (or the user test mode) that is to be con-
verted next. The address is shifted in on the first four rising
edges of SCLK. After the four mux address bits have been
received, the data on Din is ignored for the remainder of the
present serial transfer. See Table 2 in Applications Information.
SCLK
Serial Data Clock (Pin 13)
This clock input drives the internal I/O state machine to per-
form three major functions: (1) drives the data shift registers to
simultaneously shift in the next mux address from the Din pin
and shift out the previous conversion result on the Dout pin, (2)
begins sampling the analog voltage onto the RCDAC as soon as
the new mux address is available, and (3) transfers control to
the A/D conversion state machine after the last bit of the previ-
ous conversion result has been shifted out on the Dout pin.
The serial data shift registers are completely static, allowing
SCLK rates down to the DC. There are some cases, however,
that require a minimum SCLK frequency as discussed later in
this section. At least ten SCLK cycles are required for each
simultaneous data transfer. If the 16-bit format is used, SCLK
can be one continuous 16-bit stream or two intermittent 8-bit
streams. After the serial port has been initiated to perform a
serial transfer*, the new mux address is shifted in
*The serial port can be initiated in three ways: (1) a recognized CS
falling edge, (2) the end of an A/D conversion if the port is per-
forming either a 10-bit or a 16-bit “shorter-than-conversion” trans-
fer with CS active low between transfers, and (3) the 16th falling
edge of SCLK if the port is performing 16-bit “longer-than-conver-
sion” transfers with CS active low between transfers.
Table 1. Timing Diagram Selection
No. of Clocks in
Serial Transfer
Using
CS
Serial Transfer
Interval
Figure
No.
10
Yes
Don't Care
9
10
No
Don't Care
10
11 to 16
Yes
Shorter than Conversion
11
16
No
Shorter than Conversion
12
11 to 16
Yes
Longer than Conversion
13
16
No
Longer than Conversion
14


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