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MC12210D bảng dữ liệu(PDF) 8 Page - LANSDALE Semiconductor Inc.

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nhà sản xuất  LANSDALE [LANSDALE Semiconductor Inc.]
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Issue A
LANSDALE Semiconductor, Inc.
ML12210
Legacy Applications Information
LOCK DETECT
The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally
HIGH. LD is designed to be the logical NORing of the phase frequency detector's outputs UP and DOWN. See Figure 6. In typical
applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9.
OSCILLATOR INPUT
For best operation, an external reference oscillator is recommended. The signal should be AC–coupled to the OSCin pin through a cou-
pling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC–coupled signal must be between 500 and
2200 mV peak–to–peak. To optimize the phase noise of the PLL when used in this mode, the input signal amplitude should be closer to
the upper specification limit. This maximizes the slew rate of the signal as it switches against the internal voltage reference.
The device incorporates an on–chip reference oscillator/buffer so that an external parallel–resonant fundamental crystal can be connected
between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper crystal load capacitance
and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a maximum of 30 pF each including par-
asitic and stray capacitance). However, using the on–chip reference oscillator greatly increases the synthesized phase noise.
DUAL INTERNAL CHARGE PUMPS (“ANALOG SWITCH”)
Due to the pure Bipolar nature of the ML12210 design, the “analog switch” function is implemented with dual internal charge pumps.
The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output BISW as shown
in Figure 7 below. This enables the VCO to lock in a shorter amount of time.
When LE is HIGH or OPEN (“analog switch is ON”), the output of the second internal charge pump is connected to the BISW pin, and
the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is LOW,
BISW is in a high impedance state and Do output is active.
Figure 7. "Analog Switch" Block Diagram
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
LE
LPF–1
LPF–2
VCO
Figure 6. Detailed Phase Comparator Block Diagram
PHASE
FREQUENCY
DETECTOR
R
V
UP
DOWN
PHASE COMPARATOR
1
0
1
0
CHARGE
PUMP 1
Do
CHARGE
PUMP 2
BISW
LD
φR
φP
fr
fp
FC
LE


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