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AD7228LPZ bảng dữ liệu(PDF) 8 Page - Analog Devices |
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AD7228LPZ bảng dữ liệu(HTML) 8 Page - Analog Devices |
8 / 16 page Data Sheet AD7228 Rev. D | Page 7 of 15 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VD0 1 VOUT8 2 VOUT7 3 VOUT6 4 A0 24 A1 23 A2 22 WR 21 VOUT5 5 VOUT4 6 VOUT3 7 DB0 (LSB) 20 DB1 19 DB2 18 VOUT2 8 DB3 17 VOUT1 9 DB4 16 VSS 10 DB5 15 VREF 11 DB6 14 GND 12 DB7 (MSB) 13 AD7228 TOP VIEW (Not to Scale) Figure 3. 24-Lead PDIP, CERDIP, and SOIC Pin Configuration 128 27 26 2 3 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 DNC = NO CONNECT. DO NOT CONNECT TO THIS PIN. VOUT6 VOUT5 VOUT4 DNC VOUT3 VOUT2 VOUT1 WR DB0 DB1 DNC DB2 DB3 DB4 12 13 14 15 16 17 18 AD7228 TOP VIEW (Not to Scale) Figure 4. 28-Lead PLCC Pin Configuration Table 5. Pin Function Descriptions Pin No. 24-Lead PDIP, CERDIP, and SOIC 28-Lead PLCC Mnemonic Description 1 2 VDD Positive Supply Voltage This device can be operated from a supply of 10.8 V to 16.5 V. 2 3 VOUT8 Analog Output Voltage of DAC 8. 3 4 VOUT7 Analog Output Voltage of DAC 7. 4 5 VOUT6 Analog Output Voltage of DAC 6. 5 6 VOUT5 Analog Output Voltage of DAC 5. 6 7 VOUT4 Analog Output Voltage of DAC 4. 1, 8, 15, 22 DNC Do Not Connect. Do not connect to this pin. 7 9 VOUT3 Analog Output Voltage of DAC 3. 8 10 VOUT2 Analog Output Voltage of DAC 2. 9 11 VOUT1 Analog Output Voltage of DAC 1. 10 12 VSS Negative Supply Voltage. This device can be operated from a supply of −5.5 V to −4.5 V. 11 13 VREF DAC Reference Voltage Input. 12 14 GND Ground Pin. 13 16 DB7 Parallel Data Bit 7. 14 17 DB6 Parallel Data Bit 6. 15 18 DB5 Parallel Data Bit 5. 16 19 DB4 Parallel Data Bit 4. 17 20 DB3 Parallel Data Bit 3. 18 21 DB2 Parallel Data Bit 2. 19 23 DB1 Parallel Data Bit 1. 20 24 DB0 Parallel Data Bit 0. 21 25 WR Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge. The signal level on this pin must be ≤ VDD + 0.3 V. 22 26 A2 Address Pin 2. The signal level on this pin must be ≤ VDD + 0.3 V. 23 27 A1 Address Pin 1. The signal level on this pin must be ≤ VDD + 0.3 V. 24 28 A0 Address Pin 0. The signal level on this pin must be ≤ VDD + 0.3 V. |
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Mô tả tương tự - AD7228LPZ |
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