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AD7228LNZ bảng dữ liệu(PDF) 4 Page - Analog Devices |
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AD7228LNZ bảng dữ liệu(HTML) 4 Page - Analog Devices |
4 / 16 page Data Sheet AD7228 Rev. D | Page 3 of 15 SPECIFICATIONS DUAL SUPPLY VDD = 10.8 V to 16.5 V, VSS = −5 V ± 10%, GND = 0 V, VREF = 2 V to 10 V, RL = 2 kΩ, CL = 100 pF, unless otherwise noted. All specifications TMIN to TMAX, −40°C to +85°C unless otherwise noted. VOUT must be less than VDD by 3.5 V to ensure correct operation. Table 1. Parameter K and B Versions L and C Versions Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 8 8 Bits Total Unadjusted Error (TUE)1 ±2 ±1 LSB max VDD = 15 V ± 10%, VREF = 10 V Relative Accuracy ±1 ±1/2 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic Full-Scale Error2 ±1 ±1/2 LSB max Typical temperature coefficient is 5 ppm/°C with VREF = 10 V Zero Code Error at 25°C ±25 ±15 mV max Typical temperature coefficient is 30 µV/°C TMIN to TMAX ±30 ±20 mV max Minimum Load Resistance 2 2 kΩ min VOUT = 10 V REFERENCE INPUT Voltage Range 2/10 2/10 V min/V max Input Resistance 2 2 kΩ min Input Capacitance3 500 500 pF max Occurs when each DAC is loaded with all 1s AC Feedthrough −70 −70 dB typ VREF = 8 V p-p sine wave at 10 kHz DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current ±1 ±1 µA max VIN = 0 V or VDD Input Capacitance3 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE3 Voltage Output Slew Rate 2 2 V/µs min Voltage Output Settling Time Positive Full-Scale Change 5 5 µs max VREF = 10 V; settling time to ±1/2 LSB Negative Full-Scale Change 5 5 µs max VREF = 10 V; settling time to ±1/2 LSB Digital Feedthrough 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 0 V; WR = VDD Digital Crosstalk4 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 10 V; WR = 0 V POWER SUPPLIES VDD Range 10.8/16.5 10.8/16.5 V min/V max For specified performance VSS Range −4.5/−5.5 −4.5/−5.5 V min/V max For specified performance IDD Outputs unloaded; VIN = VINL or VINH at 25°C 16 16 mA max TMIN to TMAX 20 20 mA max ISS Outputs unloaded; VIN = VINL or VINH at 25°C 14 14 mA max TMIN to TMAX 18 18 mA max 1 Total unadjusted error includes zero code error, relative accuracy, and full-scale error. 2 Calculated after zero code error is adjusted out. 3 Sample tested at TA = 25°C to ensure compliance. 4 The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. |
Số phần tương tự - AD7228LNZ |
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Mô tả tương tự - AD7228LNZ |
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