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AD7228KR bảng dữ liệu(PDF) 10 Page - Analog Devices |
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10 / 16 page Data Sheet AD7228 Rev. D | Page 9 of 15 Interface Logic Information The A0, A1, and A2 address lines select which DAC accepts data from the input port. Table 6 shows the selection table for the eight DACs and Figure 8 shows the input control logic. When the WR signal is low, the input latch of the selected DAC is transparent, and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value corresponding to the data held in their respective latches. Table 6. AD7228 Truth Table Control Inputs Operation WR A2 A1 A0 High X1 X X No operation, device not selected Low Low Low Low DAC 1 transparent Low to High Low Low Low DAC 1 latched Low Low Low High DAC 2 transparent Low Low High Low DAC 3 transparent Low Low High High DAC 4 transparent Low High Low Low DAC 5 transparent Low High Low High DAC 6 transparent Low High High Low DAC 7 transparent Low High High High DAC 8 transparent 1 X means don’t care. A0 TO DAC 1 LATCH A1 A2 WR TO DAC 2 LATCH TO DAC 3 LATCH TO DAC 4 LATCH TO DAC 5 LATCH TO DAC 6 LATCH TO DAC 7 LATCH TO DAC 8 LATCH 1-OF-8 DECODER Figure 8. Input Control Logic Supply Current The AD7228 has a maximum IDD specification of 20 mA and a maximum ISS of 18 mA over the −40°C to +85°C temperature range. Figure 9 shows a typical plot of power supply current vs. temperature. VDD = +15V VSS = –5V IDD ISS 16 14 12 10 8 6 4 2 0 –2 –4 –6 –8 –10 –12 –60 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 120 140 –14 Figure 9. Power Supply Current vs. Temperature Applying the AD7228 Unipolar Output Operation Unipolar output operation is the basic mode of operation for each channel of the AD7228 and the output voltage has the same positive polarity as VREF. Connections for unipolar output operat- ion are shown in Figure 10. The AD7228 can be operated from single or dual supplies. The voltage at the reference input must never be negative with respect to GND. Failure to observe this precaution may cause parasitic transistor action and possible device destruction. The code table for unipolar output operation is shown in Table 7. VSS GND LATCH 5 DAC 5 LATCH 6 DAC 6 LATCH 7 DAC 7 LATCH 8 CONTROL LOGIC DAC 8 VOUT8 8 WR A1 A0 A2 AD7228 10 12 2 3 4 5 6 7 8 9 21 22 23 24 11 1 VOUT7 7 VOUT6 6 VOUT5 5 VOUT4 4 VOUT3 3 VOUT2 2 VOUT1 1 LATCH 1 DAC 1 LATCH 2 DAC 2 LATCH 3 DAC 3 LATCH 4 DAC 4 VREF VDD +12V TO +15V DATA BUS MSB LSB 0V OR –5V 13 20 Figure 10. Unipolar Output Circuit |
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Mô tả tương tự - AD7228KR |
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