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TS3L110DGVR bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TS3L110DGVR bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 18 page TS3L110 QUAD SPDT HIGHBANDWIDTH 10/100 BASET LAN SWITCH DIFFERENTIAL 8CHANNEL TO 4CHANNEL MULTIPLEXER/DEMULTIPLEXER SCDS176 − SEPTEMBER 2004 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION FOR ENABLE AND DISABLE TIMES CL (see Note A) TEST CIRCUIT S1 2 × VCC Open GND RL RL tPZL VOH −0.3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. 50 Ω VG1 VCC DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RL S1 V∆ CL VCC VI tPLZ/tPZL 3.3 V ± 0.3 V 2 × VCC 200 Ω GND 10 pF 0.3 V Input Generator Input Generator VCC/2 VCC/2 VO tPHZ/tPZH 3.3 V ± 0.3 V GND 200 Ω VCC 10 pF 0.3 V Output Control (VIN) 1.25 V 2.5 V VOH VOL +0.3 V VOH VOL 0 V 1.25 V tPZH tPLZ tPHZ Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 y VCC (see Note B) VOL Figure 5. Test Circuit and Voltage Waveforms |
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Mô tả tương tự - TS3L110DGVR |
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