REV. E

–8–

AD7703

DIGITAL FILTERING

The AD7703’s digital filter behaves like an analog filter, with a

few minor differences.

First, since digital filtering occurs after the analog-to-digital

conversion, it can remove noise injected during the conversion

process. Analog filtering cannot do this.

On the other hand, analog filtering can remove noise superim-

posed on the analog signal before it reaches the ADC. Digital

filtering cannot do this and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator and

digital filter, even though the average value of the signal is within

limits. To alleviate this problem, the AD7703 has overrange

headroom built into the

-

modulator and digital filter that

allows overrange excursions of 100 mV. If noise signals are larger

than this, consideration should be given to analog input filtering,

or to reducing the gain in the input channel so that a full-scale

input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V).

This will provide an overrange capability greater than 100% at

the expense of reducing the dynamic range by one bit (50%).

FILTER CHARACTERISTICS

maximum clock frequency of 4.096 MHz, the cutoff frequency

of the filter is 10 Hz and the data update rate is 4 kHz.

Figure 9 shows the filter frequency response. This is a six-pole

Gaussian response that provides 55 dB of 60 Hz rejection for a

10 Hz cutoff frequency. If the clock frequency is halved to give a

5 Hz cutoff, 60 Hz rejection is better than 90 dB.

1

10

100

FREQUENCY – Hz

20

0

–20

–40

–60

–80

–100

–120

–140

–160

f

f

f

Figure 9. Frequency Response of AD7703 Filter

Since the AD7703 contains this low-pass filtering, there is a

settling time associated with step function inputs, and data will

be invalid after a step change until the settling time has elapsed.

The AD7703 is, therefore, unsuitable for high speed multiplex-

ing, where channels are switched and converted sequentially at

high rates, as switching between channels can cause a step change

in the input. However, slow multiplexing of the AD7703 is

possible, provided that the settling time is allowed to elapse

before data for the new channel is accessed.

The output settling of the AD7703 in response to a step input

change is shown in Figure 10. The Gaussian response has fast

settling with no overshoot, and the worst-case settling time to

±0.0007% is 125 ms with a 4.096 MHz master clock frequency.

100

80

60

40

20

0

040

80

120

160

TIME – ms

Figure 10. AD7703 Step Response

USING THE AD7703

SYSTEM DESIGN CONSIDERATIONS

The AD7703 operates differently from successive approximation

ADCs or integrating ADCs. Since it samples the signal continu-

ously, like a tracking ADC, there is no need for a start convert

command. The 20-bit output register is updated at a 4 kHz rate,

and the output can be read at any time, either synchronously or

asynchronously.

CLOCKING

The AD7703 requires a master clock input, which may be an exter-

nal TTL/CMOS compatible clock signal applied to the CLKIN

pin (CLKOUT not used). Alternatively, a crystal of the correct

frequency can be connected between CLKIN and CLKOUT,

when the clock circuit will function as a crystal controlled oscillator.

Figure 11 shows a simple model of the on-chip gate oscillator

and Table II gives some typical capacitor values to be used with

various resonators.

AD7703

C2*

C1*

R1

5M

X1

3

10pF

10pF

*SEE TABLE II

2

Figure 11. On-Chip Gate Oscillator