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AD7711AN bảng dữ liệu(PDF) 3 Page - Analog Devices |
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AD7711AN bảng dữ liệu(HTML) 3 Page - Analog Devices |
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3 / 29 page  Parameter A, S Versions 1 Unit Conditions/Comments STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches £ 60 Hz 22 Bits min For Filter Notch = 100 Hz 18 Bits min For Filter Notch = 250 Hz 15 Bits min For Filter Notch = 500 Hz 12 Bits min For Filter Notch = 1 kHz Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity @ 25 ∞C ±0.0015 % FSR max Filter Notches £ 60 Hz TMIN to TMAX ±0.003 % FSR max Typically ±0.0003% Positive Full-Scale Error 2, 3 See Note 4 Excluding Reference Full-Scale Drift5 1 mV/∞C typ Excluding Reference. For Gains of 1, 2 0.3 mV/∞C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 Unipolar Offset Error2 See Note 4 Unipolar Offset Drift 5 0.5 mV/∞C typ For Gains of 1, 2 0.25 mV/∞C typ For Gains of 4, 8, 16, 32, 64, 128 Bipolar Zero Error 2 See Note 4 Bipolar Zero Drift5 0.5 mV/∞C typ For Gains of 1, 2 0.25 mV/∞C typ For Gains of 4, 8, 16, 32, 64, 128 Gain Drift 2 ppm/ ∞C typ Bipolar Negative Full-Scale Error 2 @ 25 ∞C ±0.003 % FSR max Excluding Reference TMIN to TMAX ±0.006 % FSR max Typically ±0.0006% Bipolar Negative Full-Scale Drift 5 1 mV/∞C typ Excluding Reference. For Gains of 1, 2 0.3 mV/∞C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 ANALOG INPUTS/REFERENCE INPUTS Normal Mode 50 Hz Rejection6 100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ¥ fNOTCH Normal Mode 60 Hz Rejection 6 100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ¥ fNOTCH DC Input Leakage Current @ 25 ∞C6 10 pA max TMIN to TMAX 1 nA max Sampling Capacitance6 20 pF max AIN1/REF IN Common-Mode Rejection (CMR) 100 dB min At DC and AVDD = 5 V Common-Mode Rejection (CMR) 90 dB min At DC and AVDD = 10 V Common-Mode 50 Hz Rejection 6 150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ¥ fNOTCH Common-Mode 60 Hz Rejection 6 150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ¥ fNOTCH Common-Mode Voltage Range 7 VSS to AVDD V min to V max Analog Inputs 8 Input Voltage Range 9 For Normal Operation. Depends on Gain Selected 0 to +VREF 10 max Unipolar Input Range (B/U Bit of Control Register = 1) ±VREF max Bipolar Input Range (B/U Bit of Control Register = 0) Input Sampling Rate, fS See Table III AIN2 Offset Error 2.5 mV max Removed by System Calibrations but not by Self-Calibration AIN2 Offset Drift 1.5 mV/∞C typ Reference Inputs REF IN(+) – REF IN(–) Voltage 11 +2.5 to +5 V min to V max For Specified Performance. Part Is Functional with Lower VREF Voltages Input Sampling Rate, fS fCLK IN/256 REFERENCE OUTPUT Output Voltage 2.5 V nom Initial Tolerance @ 25 ∞C ±1% max Drift 20 ppm/ ∞C typ Output Noise 30 mV typ Peak-to-Peak Noise. 0.1 Hz to 10 Hz Bandwidth Line Regulation (AVDD)1 mV/V max Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA External Current 1 mA max NOTES 1Temperature range is as follows: A Version = – 40 ∞C to +85∞C; S Version = –55∞C to +125∞C. See also Note 16. 2Applies after calibration at the temperature of interest. 3Positive full-scale error applies to both unipolar and bipolar input ranges. 4These errors will be of the order of the output noise of the part, as shown in Table I, after system calibration. These errors will be 20 mV typical after self-calibration or background calibration. 5Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6These numbers are guaranteed by design and/or characterization. 7This common-mode voltage range is allowed, provided the input voltage on AIN(+) and AIN(–) does not exceed AV DD + 30 mV and VSS – 30 mV. 8The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resis- tance depends on the selected gain (see Tables IV and V). 9The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2 input is with respect to AGND. The absolute voltage on the analog inputs should not go more positive than AVDD + 30 mV, or more negative than VSS – 30 mV. 10V REF = REF IN(+) – REF IN(–). 11The reference input voltage range may be restricted by the input voltage range requirement on the V BIAS input. AD7711–SPECIFICATIONS –2– REV. G (AVDD = +5 V 5%; DVDD = +5 V 5%; VSS = 0 V or –5 V 5%; REF IN(+) = +2.5 V; REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications TMIN to TMAX, unless otherwise noted.) |
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