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PIN ASSIGNMENTS

1

8

CLK

CS

DRB PACKAGE

(TOP VIEW)

4

CLK

DGK PACKAGE

(TOP VIEW)

SDI

GND

SDI

CS

GND

3

2

1

5

6

7

8

7

6

5

2

3

4

DAC8801

SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004

TERMINAL FUNCTIONS

PIN

NAME

DESCRIPTION

1

CLK

Clock input, positive edge triggered clocks data into shift register

Serial register input, data loads directly into the shift register MSB first. Extra leading

2

SDI

bits are ignored.

3

Internal matching feedback resistor. Connect to external op amp output.

DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance

4

versus code.

5

DAC current output. Connects to inverting terminal of external precision I to V op amp.

6

GND

Analog and digital ground

7

Posiitve power supply input. Specified range of operation 2.7 V to 5.5 V.

Chip select, active low digital input. Transfers shift register data to DAC register on

8

CS

rising edge. See Table 1 for operation.

4