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LM73605QRNPRQ1 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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LM73605QRNPRQ1 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
4 / 57 page 4 LM73605-Q1, LM73606-Q1 SNVSB12 – NOVEMBER 2017 www.ti.com Product Folder Links: LM73605-Q1 LM73606-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN I/O(1) DESCRIPTION NO. NAME 17 SYNC/MODE I Synchronization input and mode setting pin. Do not float. Tie to ground if not used. Tie to ground: auto mode, higher efficiency at light loads; Tie to logic high: forced PWM, constant switching frequency over load; Tie to external clock source: forced PWM, synchronize to the rising edge of the external clock. 18 EN I Enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to PVIN. Precision enable input allows adjustable input voltage UVLO using external resistor divider. 19 AGND G Analog ground. Ground reference for internal circuitry. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB. 20–22 PVIN P Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass capacitors CIN. CIN must be placed right next to this pin and PGND pins on PCB, and connected with short and wide traces. 23–26 PGND G Power ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP, AGND, ground side of CIN and COUT on PCB. Path to CIN must be as short as possible EP DAP G Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation path for the device. Must be used for heat sinking by soldering to ground copper on PCB. Thermal vias are preferred to improve heat dissipation to other layers. |
Số phần tương tự - LM73605QRNPRQ1 |
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Mô tả tương tự - LM73605QRNPRQ1 |
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