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ADS112U04IPW bảng dữ liệu(PDF) 5 Page - Texas Instruments

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tên linh kiện ADS112U04IPW
Giải thích chi tiết về linh kiện  16-Bit, 4-Channel, 2-kSPS, Delta-Sigma ADC With UART Interface
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ADS112U04IPW bảng dữ liệu(HTML) 5 Page - Texas Instruments

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ADS112U04
www.ti.com
SBAS838 – JANUARY 2018
Product Folder Links: ADS112U04
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
ADS112U04
UNIT
WQFN (RTE)
TSSOP (PW)
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
57.7
90.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.0
31.7
°C/W
RθJB
Junction-to-board thermal resistance
19.9
41.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
1.8
°C/W
ψJB
Junction-to-board characterization parameter
19.8
41.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
11.8
N/A
°C/W
(1)
See the Noise Performance section for more information.
(2)
Excluding error of voltage reference.
6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal
reference enabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Absolute input current
PGA disabled, gain = 1 to 4, normal mode, VIN = 0 V
±5
nA
PGA disabled, gain = 1 to 4, turbo mode, VIN = 0 V
±10
Gain = 1 to 128, VIN = 0 V
±1
Absolute input current drift
PGA disabled, gain = 1 to 4, VIN = 0 V
10
pA/°C
Gain = 1 to 128, VIN = 0 V
5
Differential input current
PGA disabled, gain = 1 to 4, normal mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±5
nA
PGA disabled, gain = 1 to 4, turbo mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±10
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±1
Differential input current drift
PGA disabled, gain = 1 to 4,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
10
pA/°C
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
2
SYSTEM PERFORMANCE
Resolution (no missing codes)
16
Bits
DR
Data rate
Normal mode
20, 45, 90, 175, 330, 600, 1000
SPS
Turbo mode
40, 90, 180, 350, 660, 1200, 2000
Noise (input-referred)(1)
Normal mode, gain = 128, DR = 20 SPS
110
nVRMS
INL
Integral nonlinearity
AVDD = 3.3 V, gain = 1 to 128, VCM = AVDD / 2,
external VREF, normal mode, best fit
–15
±6
15
ppmFSR
VIO
Input offset voltage
PGA disabled, gain = 1 to 4, differential inputs
±4
µV
Gain = 1, differential inputs, TA = 25°C
–150
±5
150
Gain = 2 to 128, differential inputs
±4
Offset drift
PGA disabled, gain = 1 to 4
0.02
µV/°C
Gain = 1 to 128
0.1
0.6
Gain error(2)
PGA disabled, gain = 1 to 4
±0.01%
Gain = 1 to 32, TA = 25°C
–0.05%
±0.01%
0.05%
Gain = 64 to 128, TA = 25°C
–0.1%
±0.015%
0.1%
Gain drift(2)
PGA disabled, gain = 1 to 4
0.5
ppm/°C
Gain = 1 to 32
0.5
2
Gain = 64 to 128
1
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