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ADC12DJ2700AAVT bảng dữ liệu(PDF) 6 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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6
ADC12DJ2700
SLVSEH9 – JANUARY 2018
www.ti.com
Product Folder Links: ADC12DJ2700
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
D6
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
D7
NCOA1
I
MSB of NCO selection control for DDC A. Tie this pin to GND if not used.
D8
ORA1
O
Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
D9, D10
DGND
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
D11
DA5–
O
High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
D12
DA1–
O
High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
E1
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
E2, E3, E4
VA19
I
1.9-V analog supply
E5
VA11
I
1.1-V analog supply
E6
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
E7
CALTRIG
I
Foreground calibration trigger input. This pin is only used if hardware calibration triggering is
selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG.
Tie this pin to GND if not used.
E8
SCS
I
Serial interface chip select active low input. The Using the Serial Interface section describes the
serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ
pullup resistor to VD11.
E9, E10
VD11
I
1.1-V digital supply
E11
DA4+
O
High-speed serialized data output for channel A, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
E12
DA0+
O
High-speed serialized data output for channel A, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
F1
CLK+
I
Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-
coupled to this input for best performance. In single-channel mode, the analog input signal is
sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled
on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination
and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN
is set to 0.
F2, F3
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
F4
VA19
I
1.9-V analog supply
F5
VA11
I
1.1-V analog supply
F6
AGND
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
F7
CALSTAT
O
Foreground calibration status output or device alarm output. Functionality is programmed through
CAL_STATUS_SEL. This pin can be left disconnected if not used.
F8
SCLK
I
Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial
programming data in and out. The Using the Serial Interface section describes the serial interface
in more detail. Supports 1.1-V and 1.8-V CMOS levels.
F9, F10
DGND
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.


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ADC12DJ2700AAVT TI1-ADC12DJ2700AAVT Datasheet
2Mb / 146P
[Old version datasheet]   ADC12DJ2700 5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
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Mô tả tương tự - ADC12DJ2700AAVT

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ADC12DJ2700 TI1-ADC12DJ2700_V01 Datasheet
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[Old version datasheet]   ADC12DJ3200QML-SP 6.4-GSPS, Single-Channel or 3.2-GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
ADC12DJ5200-SP TI-ADC12DJ5200-SP_V02 Datasheet
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