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AD7819YN bảng dữ liệu(PDF) 10 Page - Analog Devices |
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10 / 12 page REV. B AD7819 –9– PARALLEL INTERFACE The parallel interface of the AD7819 is eight bits wide. The out- put data buffers are activated when both CS and RD are logic low. At this point the contents of the data register are placed on the 8-bit data bus. Figure 15 shows the timing diagram for the par- allel port. The Parallel Interface of the AD7819 is reset when BUSY goes logic high. Care must be taken to ensure that a read operation does not occur while BUSY is high. Data read from the AD7819 while BUSY is high will be invalid. For optimum performance the read operation should end at least 100 ns (t8) prior to the falling edge of the next CONVST. 8 MSBs t1 t2 t3 tPOWER-UP EXT CONVST INT CONVST BUSY CS/RD DB7–DB0 Figure 13. Mode 1 Operation 8 MSBs t1 t3 EXT CONVST INT CONVST BUSY CS/RD DB7–DB0 tPOWER-UP Figure 14. Mode 2 Operation 8 MSBs CONVST BUSY CS DB7–DB0 t2 t3 t1 t4 t6 t7 t5 t8 RD Figure 15. Parallel Port Timing |
Số phần tương tự - AD7819YN |
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Mô tả tương tự - AD7819YN |
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